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MC100EP51DG - 

Flip-Flop, with Reset and Differential Clock, Differential, ECL, Positive Edge, D, 370 ps, 3 GHz

MC100EP51DG - Flip-Flop, with Reset and Differential Clock, Differential, ECL, Positive Edge, D, 370 ps, 3 GHz

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Manufacturer Part No:
MC100EP51DG
Order Code:
1607712
Technical Datasheet:
MC100EP51DG   Datasheet
See all Technical Docs

Product Overview

The MC100EP51DG is a differential clock D-type Flip-flop with reset. It is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is low and is transferred to the slave and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLK\ input will be biased at VCC/2. The 100 series contains temperature compensation.
  • Open input default state
  • Safety clamp on inputs

Applications

Industrial

Product Information

:
-
:
D
:
370ps
:
3GHz
:
50mA
:
SOIC
:
8Pins
:
Positive Edge
:
Differential, ECL
:
3V
:
5.5V
:
100EP
:
-
:
-40°C
:
85°C
:
-
:
-
:
-
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