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Development Kit, ispClock5600A's PLL, Header For User I/O, JTAG Programming Cable Connector

PAC-SYSCLK5620AV - Development Kit, ispClock5600A's PLL, Header For User I/O, JTAG Programming Cable Connector

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PAC-SYSCLK5620AV   Datasheet
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Product Information

Lattice Semiconductor
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Product Overview

The PAC-SYSCLK5620AV is an evaluation board which allows the designer to quickly configure and evaluate the ispClock5620 on a fully assembled printed circuit board. The four layer board supports a 100 pin TQFP package, a header for user I/O and a JTAG programming cable connector. SMA connectors are installed to provide high signal integrity access to selected high speed I/O signals. JTAG programming signals can be generated by using an ispDOWNLOAD programming cable connected between the evaluation board and a PC's parallel (printer) port. All user programmable features of the ispPAC-CLK5620A can be easily configured using PAC designer software. The ispDOWNLOAD cable can be used to program the ispClock5620A which is provided on the evaluation board. This cable plugs into a PC compatible's parallel port connector and includes active buffer circuitry inside its DB 25 connector housing.
  • A header for user I/O
  • JTAG programming cable connector
  • SMA connectors
  • Reset switch
  • Several LEDs are provided on the board to indicate proper function and as aids to debugging
  • Supply voltage range from 4.5V to 5.5V


Embedded Design & Development


IspClock evaluation board, ispDOWNLOAD cable.

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$480.37 ( $528.41 Inc. GST)

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